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fn8194 rev 2.00 page 1 of 20 october 12, 2006 fn8194 rev 2.00 october 12, 2006 X9418 low noise/low power/2-wire bus dual digitally controlled potent iometers (xdcp?) datasheet features ? two potentiometers in one package ? 2-wire serial interface ? register oriented format direct read/write/transfer wiper position store as many as fo ur positions per potentiometer ? power supplies v cc = 2.7v to 5.5v v+ = 2.7v to 5.5v vC = -2.7v to -5.5v ? low power cmos standby current < 1a ideal for battery operated applications ? high reliability enduranceC100,000 data changes per bit per register register data retentionC100 years ? 8-bytes of nonvolatile memory ?2.5k ? , 10k ? resistor array ? resolution: 64 taps each potentiometer ? 24-pin plastic dip, 24-lead tssop and 24-lead soic packages ? pb-free plus anneal ava ilable (rohs compliant) description the X9418 integrates two digitally controlled potentiometers (xdcp) on a monolithic cmos integrated microcircuit. the digitally controlled potentiometer is implemented using 63 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the 2-wire bus interface. each potentiometer has associated with it a volatile wiper coun ter register (wcr) and 4 nonvolatile data registers (dr0:dr3) that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array through the switches. power up recalls the contents of dr0 to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. block diagram r0 r1 r2 r3 resistor array xdcp1 v h1 /r h1 v l1 /r l1 r0 r1 r2 r3 wiper counter register (wcr) interface and control circuitry scl sda a0 a1 a2 a3 v h0 /r h0 v l0 /r l0 data 8 v w0 /r w0 v w1 /r w1 wiper counter register (wcr) wp v cc v ss v+ v- 1 2 7 5 ( & 2 0 0 ( 1 ' ( ' ) 2 5 1 ( : ' ( 6 , * 1 6 1 2 5 ( & 2 0 0 ( 1 ' ( ' 5 ( 3 / $ & ( 0 ( 1 7 f r q w d f w r x u 7 h f k q l f d o 6 x s s r u w & h q w h u d w , 1 7 ( 5 6 , / r u z z z l q w h u v l o f r p w v f
X9418 fn8194 rev 2.00 page 2 of 20 october 12, 2006 pin descriptions host interface pins serial clock (scl) the scl input is used to cloc k data into and out of the X9418. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. device address (a 0 - a 3 ) the address inputs are used to set the least significant 4 bits of the 8-bit slave add ress. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9418. a maximum of 16 devices may occupy the 2- wire serial bus. potentiometer pins v h /r h (v h0 /r h0 - v h1 /r h1 ), v l /r l (v l0 /r l0 - v l1 /r l1 ) the v h /r h and v l /r l inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. v w /r w (v w0 /r w0 - v w1 /r w1 ) the wiper outputs are equivalent to the wiper output of a mechanical potentiometer. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the data registers. analog supplies v+, v- the analog supplies v+, v- are the supply voltages for the xdcp analog section. ordering information part number part marking v cc limits (v) potentiomet er organization (k ? ) temperatu re range (c) package pkg. dwg. # X9418wv24* X9418wv 5 10% 10 0 to +70 24 ld tssop (4.4mm) mdp0044 X9418wv24z* (note) X9418wv z 0 to +70 24 ld tssop (4.4mm) (pb-free ) mdp0044 X9418wp24i-2.7 X9418wp g 2.7 to 5.5 10 -40 to +85 24 ld pdip e24.6 X9418ws24i-2.7 X9418ws g -40 to +85 24 ld soic (300mil) m24.3 X9418ws24iz-2.7 (note) X9418ws zg -40 to +85 24 ld soic (300mil) ( pb-free) m24.3 X9418wv24-2.7* X9418wv f 0 to +70 24 ld tssop (4.4mm) mdp0044 X9418wv24z-2.7* (note) X9418wv zf 0 to +70 24 ld tssop (4.4mm) (pb -free) mdp0044 X9418wv24i-2.7 X9418wv g -40 to +85 24 ld tssop (4.4mm) mdp0044 X9418wv24iz-2.7 (note) X9418wv zg -40 to +85 24 ld tssop (4.4mm) ( pb-free) mdp0044 X9418ys24-2.7 X9418ys f 2.5 0 to +70 24 ld soic (300mil) m24.3 X9418ys24z-2.7 (note) X9418ys zf 0 to +70 24 ld soic (300mil) (pb- free) m24.3 X9418ys24i-2.7 X9418ys g -40 to +85 24 ld soic (300mil) m24.3 X9418ys24iz-2.7 (note) X9418ys zg -40 to +85 24 ld soic (300mil) ( pb-free) m24.3 X9418yv24i-2.7* X9418yv g -40 to +85 24 ld tssop (4.4mm) mdp0044 X9418yv24iz-2.7* (note) X9418yv zg -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compo unds/die attach materials and 10 0% matte tin plate termination finish, which are rohs compliant and compatib le with both snpb and pb-free so ldering operations. intersil pb -free products are msl classified at pb-free peak ref low temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020.
X9418 fn8194 rev 2.00 page 3 of 20 october 12, 2006 pin configuration pin names principles o f operation the X9418 is a highly integrated microcircuit incorporating two resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the xdcp potentiometers. serial interface the X9418 supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will a lways initiate data transfers and provide the clock for both transmit and receive operations. therefore, the X9418 will be considered a slave device in all applications. clock and data conventions data states on the sda line can change only during scl low periods (t low ). sda state changes during scl high are reserved for indicating start and stop conditions. start condition all commands to the X9418 are preceded by the start condition, which is a high to low transition of sda while scl is high (t high ). the X9418 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition is met. stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. acknowledge acknowledge is a software convention used to provide a positive handshake betwee n the master and slave devices on the bus to indica te the successful receipt of data. the transmitting device, either the master or the slave, will release the sda bus after transmitting eight bits. the master generates a ninth clock cycle and during this period the receiver pulls the sda line low to acknowledge that it successfully received the eight bits of data. symbol description scl serial clock sda serial data a0 - a3 device address v h0 /r h0 - v h1 /r h1 , v l0 /r l0 - v l1 /r l1 potentiometer pins (terminal equivalent) v w0 /r w0 - v w1 /r w1 potentiometer pins (wiper equivalent) wp hardware write protection v+,v- analog supplies v cc system supply voltage v ss system ground nc no connection v cc r l0 /v l0 r h0 /v h0 wp sda a1 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 5 v+ nc nc nc a0 nc a3 scl nc nc dip/soic X9418 v ss r w0 /v w0 14 13 11 12 a2 r l1 /v l1 r h1 /v h1 r w1 /v w1 nc v- sda a1 r l1 /v l1 v ss nc nc 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 wp a2 v w0 /r w0 v h0 /r h0 v l0 /r l0 v cc nc nc nc v+ X9418 a3 r h1 /v h1 14 13 11 12 r w1 /v w1 nc v- scl a0 nc tssop
X9418 fn8194 rev 2.00 page 4 of 20 october 12, 2006 the X9418 will respond with an acknowledge after recognition of a start condit ion and its slave address and once again after successful receipt of the command byte. if the command is followed by a data byte the X9418 will respond with a final acknowledge. array description the X9418 is comprised of two resistor arrays. each array contains 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (v h /r h and v l /r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (v w /r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by the wiper counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixty-four switches. the wcr may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the wcr. these data registers and the wcr can be read and written by the host system. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are the device type identifier (refer to figure 1 below). for the X9418 this is fixed as 0101[b]. figure 1. slave address the next four bits of the slave address are the device address. the physical device address is defined by the state of the a 0 - a 3 inputs. the X9418 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9418 to respond with an acknowledge. the a 0 - a 3 inputs can be actively driven by cmos input signals or tied to v cc or v ss . acknowledge polling the disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5m s eeprom write cycle time. once the stop condition is issued to indicate the end of the nonvolatile write command the X9418 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the device slave address. if the X9418 is still busy with the write operation no ack will be returned. if the X9418 has completed the write operation an ack will be returned, and the mast er can then proceed with the next operation. flow 1. ack polling sequence instruction structure the next byte sent to the x 9418 contains the instruction and register pointer informati on. the four most significant bits are the instruction. the next four bits point to one of the two pots and when applicable they point to one of four associated registers. the format is shown figure 2. 1 00 a3 a2 a1 a0 device type identifier device address 1 nonvolatile write command completed enter ack polling issue start issue slave address ack returned? further operation? issue instruction issue stop no yes yes proceed issue stop no proceed
X9418 fn8194 rev 2.00 page 5 of 20 october 12, 2006 figure 2. instruction byte format the four high order bits define the instruction. the next two bits (r1 and r0) select on e of the four registers that is to be acted upon when a register oriented instruction is issued. the last bits (p0) select which one of the two potentiometers is to be affected by the instruction. bit 1 is defined to be 0. four of the nine instructions end with the transmission of the instruction byte. the basic sequence is illustrated in figure 3. these two-byte instructions exchange data between the wiper counter register and one of the data registers. a transfer from a data register to a wiper counter register is essentially a write to a static ram. the response of the wiper to this action will be delayed t wrl . a transfer from the wiper counter register (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between both of the potent iometers and one of their associated registers. four instructions require a three-byte sequence to complete. these instructions transfer data between the host and the X9418; either between the host and one of the data registers or direct ly between the host and the wiper counter register. these instructions are: read wiper counter register (read the current wiper position of the selected pot), write wiper counter register (change current wiper position of the selected pot), read data register (read the contents of the selected nonvolatile register) and write data register (write a new value to the selected data register). the sequence of operations is shown in figure 4. the increment/decrement command is different from the other commands. once the command is issued and the X9418 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. for each scl clock pulse (t high ) while sda is high, the se lected wiper will move one resistor segment towards the v h /r h terminal. similarly, for each scl clock pulse while sda is low, the selected wiper will move one resistor segment towards the v l /r l terminal. a detailed illustration of the sequence and timing for this operation are shown in figures 5 and 6 respectively. figure 3. two-byte instruction sequence i1 i2 i3 i0 r1 r0 0 p0 wiper counter register select register select instructions s t a r t 0101a3a2a1a0 a c k i3 i2 i1 i0 r1 r0 0 p0 a c k scl sda s t o p
X9418 fn8194 rev 2.00 page 6 of 20 october 12, 2006 table 1. instruction set note: (7) 1/0 = data is one or zero figure 4. three-byte instruction sequence figure 5. increment/decrement instruction sequence instruction instruction set operation i 3 i 2 i 1 i 0 r 1 r 0 p 1 p 0 read wiper counter register 1 0 0 1 0 0 0 1/0 read the contents of the wiper counter register pointed to by p 0 write wiper counter register 1 0 1 0 0 0 0 1/0 write new value to the wiper counter register pointed to by p 0 read data register 1 0 1 1 1/0 1/0 0 1/0 read the contents of the data register pointed to by p 0 and r 1 - r 0 write data register 1 1 0 0 1/0 1/0 0 1/0 write new value to the data register pointed to by p 0 and r 1 - r 0 xfr data register to wiper counter register 1 1 0 1 1/0 1/0 0 1/0 transfer the contents of the data register pointed to by p 0 and r 1 - r 0 to its associated wiper counter register xfr wiper counter register to data register 1 1 1 0 1/0 1/0 0 1/0 transfer the contents of the wiper counter register pointed to by p 0 to the data register pointed to by r 1 - r 0 global xfr data registers to wiper counter registers 0 0 0 1 1/0 1/0 0 0 transfer the contents of the data registers pointed to by r 1 - r 0 of both pots to their respective wiper counter registers global xfr wiper count- er registers to data reg- ister 1 0 0 0 1/0 1/0 0 0 transfer the contents of both wiper counter registers to their respective data registers pointed to by r 1 - r 0 of both pots increment/decrement wiper counter register 0 0 1 0 0 0 0 1/0 enable increment/decrement of the wiper counter register pointed to by p 0 s t a r t 0 1 0 1 a3 a2 a1 a0 a c k i3 i2 i1 i0 r1 r0 0 p0 a c k scl sda s t o p a c k 0 0 d5 d4 d3 d2 d1 d0 s t a r t 0 1 0 1 a3 a2 a1 a0 a c k i3 i2 i1 i0 r0 0 p0 a c k scl sda s t o p x x i n c 1 i n c 2 i n c n d e c 1 d e c n r1
X9418 fn8194 rev 2.00 page 7 of 20 october 12, 2006 figure 6. increment/decrement timing limits figure 7. acknowledge response from receiver scl sda v w /r w inc/dec cmd issued voltage out t wrid scl from data output from transmitter 1 89 start acknowledge master data output from receiver
X9418 fn8194 rev 2.00 page 8 of 20 october 12, 2006 figure 8. detailed potent iometer block diagram detailed operation both xdcp potentiometers share the serial interface and share a common architecture. each potentiometer has a wiper counter register and four data registers. a detailed discussion of the register organization and array operation follows. wiper counter register the X9418 contains two wiper counter registers, one for each xdcp potentiometer. the wiper counter register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty- four switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via t he write wiper counter register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register instruction (parallel load); it can be modified one step at a time by the increment/decrement instruction. finally, it is loaded with the contents of its data register zero (dr0) upon power-up. the wcr is a volatile regist er; that is, its contents are lost when the X9418 is powered-down. although the register is automatically loaded with the value in dr0 upon power-up, it should be noted this may be different from the value present at power-down. data registers each potentiometer has four nonvolatile data registers. these can be read or writt en directly by the host and data can be transferred between any of the four data registers and the wiper counter register. it should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. register descriptions data registers, (6-bit), nonvolatile four 6-bit data registers for each xdcp. (eight 6-bit registers in total). ? {d5~d0}: these bits are for general purpose not volatile data storage or for storage of up to four different wiper values. the c ontents of data register 0 are automatically moved to the wiper counter register on power-up. serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input wiper counter register inc/dec logic up/dn clk modified scl up/dn v h /r h v l /r l v w /r w if wcr = 00[h] then v w /r w = v l /r l if wcr = 3f[h] then v w /r w = v h /r h 8 6 c o u n t e r d e c o d e (wcr) d5 d4 d3 d2 d1 d0 nv nv nv nv nv nv (msb) (lsb)
X9418 fn8194 rev 2.00 page 9 of 20 october 12, 2006 wiper counter regist er, (6-bit), volatile one 6-bit wiper counter register for each xdcp. (four 6- bit registers in total.) ? {d5~d0}: these bits specif y the wiper position of the respective xdcp. the wiper counter register is loaded on power-up by the value in data register 0. the contents of the wcr can be loaded from any of the other data register or directly. the contents of the wcr can be saved in a dr. instruction format notes: (1) ?mack?/?sack?: stands for the ack nowledge sent by the master/slave. (2) ?a3 ~ a0?: stands for the device addresses sent by the master. (3) ?x?: indicates that it is a ?0? for testing pu rpose but physicall y it is a ?don?t care? condition. (4) ?i?: stands for the increment operation, sda held high during active scl phase (high). (5) ?d?: stands for the decrement operation, sd a held low during active scl phase (high). read wiper count er register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) xfr data register (dr) to wi per counter register (wcr) wp5 wp4 wp3 wp2 wp1 wp0 vvvvvv (msb) (lsb) s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k wiper position (sent by slave on sda) m a c k s t o p 0101 a 3 a 2 a 1 a 0 1001000 p 0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k wiper position (sent by master on sda) s a c k s t o p 0101 a 3 a 2 a 1 a 0 1010000 p 0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k wiper position/data (sent by slave on sda) m a c k s t o p 0101 a 3 a 2 a 1 a 0 1011 r 1 r 0 0 p 0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k wiper position/data (sent by master on sda) s a c k s t o p high-voltage write cycle 0101 a 3 a 2 a 1 a 0 1100 r 1 r 0 0p0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k s t o p 0101 a 3 a 2 a 1 a 0 1101 r 1 r 0 0 p 0
X9418 fn8194 rev 2.00 page 10 of 20 october 12, 2006 xfr wiper counter register (wcr) to data register (dr) increment/decrement wipe r counter register (wcr) global xfr data register (dr) t o wiper counter register (wcr) global xfr wiper counter registe r (wcr) to data register (dr) symbol table guidelines for calculating typical values of bus pull-up resistors s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k s t o p high-voltage write cycle 0101 a 3 a 2 a 1 a 0 1110 r 1 r 0 0 p 0 s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k increment/decrement (sent by master on sda) s t o p 0101 a 3 a 2 a 1 a 0 0010000 p 0 i/ d i/ d .... i/ d i/ d s t a r t device type identifier device addresses s a c k instruction opcode dr addresses s a c k s t o p 0101 a 3 a 2 a 1 a 0 0001 r 1 r 0 00 s t a r t device type identifier device addresses s a c k instruction opcode dr addresses s a c k s t o p high-voltage write cycle 0101 a 3 a 2 a 1 a 0 1000 r 1 r 0 00 waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k) bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k ?
X9418 fn8194 rev 2.00 page 11 of 20 october 12, 2006 absolute maximum ratings temperature under bias .................... -65c to +135c storage temperature ......................... -65c to +150c voltage on sda, scl or any address input with respect to v ss ......................... -1v to +7v voltage on v+ (referenced to v ss )........................ 10v voltage on v- (referenced to v ss )........................-10v (v+) - (v-) .............................................................. 12v any v h /r h , v l /r l , v w /r w ........................... v- to v+ lead temperature (soldering, 10 seconds)...... +300c i w (10 seconds)..................................................6ma comment stresses above those liste d under ?absolute maximum ratings? may cause perman ent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sectio ns of this specification) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog characteristics (over recommended operating condi tions unless otherwise stated.) symbol parameter limits test conditions min. typ. max. unit end to end resistance tolerance -20 +20 % power rating 50 mw +25 c, each pot i w wiper current -3 +3 ma r w wiper resistance 150 250 ? wiper current = ? 1ma, v+, v- = 3v 40 100 ? wiper current = ? 1ma, v+, v- = 5v v+ voltage on v+ pin X9418 +4.5 +5.5 v X9418-2.7 +2.7 +5.5 v- voltage on v- pin X9418 -5.5 -4.5 v X9418-2.7 -5.5 -2.7 v term voltage on any v h /r h , v l /r l or v w /r w v- v+ v noise -120 dbv ref: 1khz resolution (4) 1.6 % see note 4 absolute linearity (1) -1 +1 mi (3) v w(n)(actual) - v w(n)(expected) (4) relative linearity (2) -0.2 +0.2 mi (3) v w(n + 1 - [v w(n) + mi ] (4) temperature coefficient of r total ? 300 ppm/ ? c see note 4 ratiometric temperature coefficient 20 ppm/c see note 4 c h /c l /c w potentiometer capacitances 10/10/25 pf see circuit #3, spice macromodel i al r h , r l , r w leakage current 0.1 10 a v in = v- to v+. device is in stand-by mode. recommended operating conditions temp min. max. commercial 0 c+70 c industrial -40 c+85 c device supply voltage (v cc ) limits X9418 5v ?? 10% X9418-2.7 2.7v to 5.5v
X9418 fn8194 rev 2.00 page 12 of 20 october 12, 2006 d.c. operating characteristics (over the recommended operating cond itions unless otherwise specified.) notes: (1) absolute linearity is utilized to determ ine actual wiper voltage versus expected vo ltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to deter mine the actual change in voltage between two su ccessive tap positions when used as a potentiometer. it is a measure of the error in step size. (3) mi = rtot/63 or (r h - r l )/63, single pot endurance and data retention capacitance power-up timing power up requirements (power up sequencing can affect correct recall of the wiper registers) the preferred power-on sequence is as follows: first v cc , then v+ and v-, and then the potentiometer pins, r h , r l , and r w . voltage should not be applied to the potentiometer pins before v+ or v- is applied. the v cc ramp rate specification should be met, and any glitches or slope changes in the v cc line should be held to <100mv if possible. if v cc powers down, it should be held below 0.1v for more than 1 second before powering up again in order for proper wiper register recall. also, v cc should not reverse polarity by more th an 0.5v. recall of wiper position will not be complete until v cc , v+ and v- reach their final value. notes: (4) this parameter is periodically sampled and not 100% tested (5) t pur and t puw are the delays required from the time the third (last) power supply (v cc , v+ or v-) is stable until the specific instruction can be issued. these parameters are periodically sampled and not 100% tested. (6) this is a tested or guaranteed paramet er and should only be used as a guidance. symbol parameter limits test conditions min. typ. max. unit i cc1 v cc supply current (nonvolatile write) 1maf scl = 400khz, sda = open, other inputs = v ss i cc2 v cc supply current (move wiper, write, read) 100 a f scl = 400khz, sda = open, other inputs = v ss i sb v cc current (standby) 1 a scl = sda = v cc , addr. = v ss i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage -0.5 v cc x 0.1 v v ol output low voltage 0.4 v i ol = 3ma parameter min. unit minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. unit test conditions c i/o (4) input/output capacitance (sda) 8 pf v i/o = 0v c in (4) input capacitance (a0, a1, a2, a3, and scl) 6 pf v in = 0v symbol parameter min. typ. max. unit t pur (5) power-up to initiation of read operation 1 ms t puw (5) power-up to initiation of write operation 5 ms t r v cc (6) v cc power up ramp rate 0.2 50 v/msec
X9418 fn8194 rev 2.00 page 13 of 20 october 12, 2006 a.c. test conditions equivalent a.c. load circuit circuit #3 spice macro model ac timing (over recommended operating conditions) i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 5v 1533 ? 100pf sda output 10pf r h r total c h 25pf c w c l 10pf r w r l symbol parameter min. max. unit f scl clock frequency 400 khz t cyc clock cycle time 2500 ns t high clock high time 600 ns t low clock low time 1300 ns t su:sta start setup time 600 ns t hd:sta start hold time 600 ns t su:sto stop setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat sda data input hold time 30 ns t r scl and sda rise time 300 ns t f scl and sda fall time 300 ns t aa scl low to sda data output valid time 900 ns t dh sda data output hold time 50 ns t i noise suppression time constant at scl and sda inputs 50 ns t buf bus free time (prior to any transmission) 1300 ns t su:wpa wp , a0, a1, a2 and a3 setup time 0 ns t hd:wpa wp , a0, a1, a2 and a3 hold time 0 ns
X9418 fn8194 rev 2.00 page 14 of 20 october 12, 2006 high-voltage write cycle timing xdcp timing note: (8) a device must internally provide a ho ld time of at least 300ns for the sda si gnal in order to bridge the undefined region of the falling edge of scl. timing diagrams start and stop timing g input timing output timing symbol parameter typ. max. unit t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. unit t wrpo wiper response time after the third (last) power supply is stable 10 s t wrl wiper response time after instruction issued (all load instructions) 10 s t wrid wiper response time from an active scl/sc k edge (increment/decrement instruction) 10 s t su:sta t hd:sta t su:sto scl sda t r (start) (stop) t f t r t f scl sda t high t low t cyc t hd:dat t su:dat t buf scl sda t dh t aa
X9418 fn8194 rev 2.00 page 15 of 20 october 12, 2006 xdcp timing (for all load instructions) xdcp timing (for incremen t/decrement instruction) write protect and device address pins timing scl sda v w /r w (stop) lsb t wrl scl sda v w /r w t wrid wiper register address inc/dec inc/dec sda scl ... ... ... wp a0, a1 a2, a3 t su:wpa t hd:wpa (start) (stop) (any instruction)
X9418 fn8194 rev 2.00 page 16 of 20 october 12, 2006 applications information basic configurations of electronic potentiometers application circuits v r v w /r w +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current 121,19(57,1*$03/,), (5 92/7$*(5(*8/$725 2))6(792/7$*($'-8670(17 &203$5$725:,7++<67(5(6,6 + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + ? v s v o r 2 r 1 } }
X9418 fn8194 rev 2.00 page 17 of 20 october 12, 2006 application circuits (continued) inverting amplifier equivalent l-r circuit + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency ? r 1 , r 2 , c amplitude ? r a , r b c attenuator filter + ? v s v o r 3 r 1 v o = g v s -1/2 ? g ? +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 ? rc) r 2 r 4 all r s = 10k ? + ? v s r 2 r 1 r c v o
X9418 fn8194 rev 2.00 page 18 of 20 october 12, 2006 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in ca se of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not in clude dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e24.6 (jedec ms-011-aa issue b) 24 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.150 1.290 29.3 32.7 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n24 249 rev. 0 12/93
X9418 fn8194 rev 2.00 page 19 of 20 october 12, 2006 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m ? m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 ? 0 o 8 o 0 o 8 o - rev. 0 12/93
fn8194 rev 2.00 page 20 of 20 october 12, 2006 X9418 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2005-2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail x end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol 14 ld 16 ld 20 ld 24 ld 28 ld tolerance a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. e 12/02 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.

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